Marc Boulé
Professeur enseignant
Eng.
Department
Département des enseignements généraux
Degrees
B.Ing. (ÉTS), M.Ing., Ph.D. (McGill)
Office
B-2560
Email
Overview
Expertise
- Electromagnetism
- Finite element method
Courses and supervision
Publications
Publications
- Jean-Samuel Chenard, Stephan Bourduas, Nathaniel Azuelos, Marc Boulé, Zeljko Zilic. 2007 « Hardware assertion checkers in on-line detection of faults in a hierarchical-ring network-on-chip ». Affiche présentée lors de la conférence : Design, Automation and Test in Europe Conference (DATE 2007) (Nice, France, Apr. 16-20, 2007)
- Marc Boulé, Zeljko Zilic. 2005 « Incorporating efficient assertion checkers into hardware emulation ». Affiche présentée lors de la conférence : TEXPO 2005 (Ottawa, ON, Canada, Oct. 2005)
- Marc Boulé, Zeljko Zilic. 2003 « FPGA hardware acceleration: From chess playing to automated theorem proving ». Affiche présentée lors de la conférence : Micronet 2003 (Toronto, ON, Canada, Sept. 2003)
- Marc Boulé, Zeljko Zilic. 2002 « An FPGA move generator for the game of chess ». Affiche présentée lors de la conférence : TEXPO 2002 (Ottawa, ON, Canada, June 2002)
- Marc Boulé, Atanu Chattopadhyay, Man-wah Chiang, Stuart McCracken, Zeljko Zilic. 2001 « Overview of MCSoC2: A second generation managed clock system on chip ». Affiche présentée lors de la conférence : TEXPO 2001 (Ottawa, ON, Canada, June 2001)
- Marc Boulé. 2026 « RLC parameters of a two-wire line with the finite element method ». Canadian Journal of Physics = Revue canadienne de physique vol. 104
- Marc Boulé. 2024 « DC power transported by two infinite parallel wires ». American Journal of Physics vol. 92 , nº 1. p. 14-22
- Jason G. Tong, Marc Boulé, Zeljko Zilic. 2013 « Test compaction techniques for assertion-based test generation ». ACM Transactions on Design Automation of Electronic Systems vol. 19 , nº 1
- Katell Morin-Allory, Marc Boulé, Dominique Borrione, Zeljko Zilic. 2010 « Validating assertion language rewrite rules and semantics with automated theorem provers ». IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 29 , nº 9. p. 1436-1448
- Jason G. Tong, Marc Boulé, Zeljko Zilic. 2010 « Defining and providing coverage for assertion-based dynamic verification ». Journal of Electronic Testing: Theory and Applications vol. 26 , nº 2. p. 211-225
- Marc Boulé, Zeljko Zilic. 2008 « Automata-based assertion-checker synthesis of PSL properties ». ACM Transactions on Design Automation of Electronic Systems vol. 13 , nº 1
- M. Boulé, J. S. Chenard, Z. Zilic. 2007 « Debug enhancements in assertion-checker generation ». IET Computers and Digital Techniques vol. 1 , nº 6. p. 669-677
- Marc Boulé, Zeljko Zilic. 2002 « An FPGA move generator for the game of chess ». Journal of International Computer Games Association vol. 25 , nº 2. p. 85-94
- Marc Boulé, Zeljko Zilic. 2011-09-20 « Automata unit, a tool for designing checker circuitry and a method of manufacturing hardware circuitry incorporating checker circuitry ». Brevet américain US 8,024,691.
- Marc Boulé. 2008 « L'outil MBAC et la synthèse de circuits vérificateurs d’assertions ». Communication lors de la conférence : Laboratoire TIMA-VDS, Institut National Polytechnique de Grenoble (Grenoble, France, Fév. 2008)
- Marc Boulé, Zeljko Zilic. 2005 « Incorporating efficient assertion checkers into hardware emulation ». Communication lors de la conférence : Séminaire ReSMiQ 2005 (Montréal, QC, Canada, Sept. 2005)
- Marc Boulé, Zeljko Zilic. 2003 « FPGA hardware acceleration: From chess playing to automated theorem proving ». Communication lors de la conférence : Micronet 2003 (Toronto, ON, Canada, Sept. 2003)
- Marc Boulé, Atanu Chattopadhyay, Man-wah Chiang, Stuart McCracken, Zeljko Zilic. 2001 « Overview of MCSoC2: A second generation managed clock system on chip ». Communication lors de la conférence : TEXPO 2001 (Ottawa, ON, Canada, June 2001)
- Jason G. Tong, Marc Boulé, Zeljko Zilic. 2016 « Accelerating assertion assessment using GPUs ». IEEE International High-Level Design, Validation and Test Workshop (HLDVT) (Santa Cruz, CA, USA, Oct. 7-8, 2016) IEEE
- Marc Boulé. 2014 « The role of Finite Element Method software in the teaching of electromagnetics ». Fourth Interdisciplinary Engineering Design Education Conference (IEDEC) (Santa Clara, CA, USA, Mar. 3, 2014) IEEE
- J. G. Tong, Marc Boulé, Z. Zilic. 2013 « Efficient Data Encoding for Improving Fault Simulation Performance on GPUs ». 2013 4th International Symposium on Electronic System Design (Singapore, Singapore, Dec. 12-13, 2013) IEEE Computer Society
- J. G. Tong, Marc Boulé, Z. Zilic. 2013 « Mu-GSIM: A mutation testing simulator on GPUs ». Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) (Penang, Malaysia, Aug. 26-28, 2013) IEEE
- Jason G. Tong, Marc Boulé, Zeljko Zilic. 2012 « Assertion clustering for compacted test sequence generation ». 2012 13th International Symposium on Quality Electronic Design (ISQED 2012) (Santa Clara, CA, USA, Mar. 19-21, 2012) IEEE
- Jason G. Tong, Danny Sarraf, Marc Boulé, Zeljko Zilic. 2011 « Generating compact assertions for control-based logic signals ». IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) (Seoul, Korea, Aug. 07-10, 2011) IEEE
- Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boulé, Zeljko Zilic. 2009 « MYGEN : AAA Automata-based on-line test generator for assertion-based verification ». Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) (Boston, MA, USA, May 10-12, 2009) Association for Computing Machinery
- Jason G. Tong, Marc Boulé, Zeljko Zilic. 2009 « Airwolf-TG: A test generator for assertion-based dynamic verification ». IEEE International High Level Design Validation and Test Workshop (San Francisco, CA, USA, Nov. 04-06, 2009) IEEE
- Marc Boulé, Zeljko Zilic. 2008 « Assertion checkers - Enablers of quality design ». 1st Microsystems and Nanoelectronics Research Conference (MNRC) (Ottawa, ON, Canada, Oct. 15, 2008) IEEE
- Katell Morin-Allory, Marc Boulé, Dominique Borrione, Zeljko Zilic. 2008 « Proving and disproving assertion rewrite rules with automated theorem provers ». IEEE International High Level Design Validation and Test Workshop (Incline Village, NV, USA, Nov. 19-21, 2008) IEEE
- Marc Boulé, Jean-Samuel Chenard, Zeljko Zilic. 2007 « Assertion checkers in verification, silicon debug and in-field diagnosis ». 8th International Symposium on Quality Electronic Design (ISQED'07) (San Jose, CA, USA, Mar. 26-28, 2007) IEEE
- Marc Boulé, Zeljko Zilic. 2007 « Efficient automata-based assertion-checker synthesis of SEREs for hardware emulation ». Asia and South Pacific Design Automation Conference (Yokohama, Japan, Jan. 23-26, 2007) IEEE
- Marc Boulé, Jean-Samuel Chenard, Zeljko Zilic. 2006 « Adding debug enhancements to assertion checkers for hardware emulation and silicon debug ». International Conference on Computer Design (San Jose, CA, USA, Oct. 01-04, 2006) IEEE
- Marc Boulé, Zeljko Zilic. 2006 « Efficient automata-based assertion-checker synthesis of PSL properties ». IEEE International High Level Design Validation and Test Workshop (Monterey, CA, USA, Nov. 08-10, 2006) IEEE
- Marc Boulé, Zeljko Zilic. 2005 « Incorporating efficient assertion checkers into hardware emulation ». International Conference on Computer Design (San Jose, CA, USA, Oct. 02-05, 2005) IEEE
- M. Boulé, Z. Zilic. 2002 « An FPGA based move generator for the game of chess ». IEEE 2002 Custom Integrated Circuits Conference (Orlando, FL, USA, May 15, 2002) IEEE
- André St-Amand, Marc Boulé. 2016 « Physique des ondes ». Montréal : Presses de l'Université du Québec. 432 p.
- Marc Boulé, Zeljko Zilic. 2008 « Generating hardware assertion checkers: For hardware verification, emulation, post-fabrication debugging and on-line monitoring ». : Springer. 279 p.
- Marc Boulé. 2008 « Assertion-checker synthesis for hardware verification, in-circuit debugging and on-line monitoring ». 238 p.Thèse de doctorat. Montréal, McGill.
- Marc Boulé. 2002 « An FPGA move generator for the game of chess ». 115 p.Mémoire de maîtrise. Montréal, McGill.