Hardware Autogeneration for Error-Correction Solutions

Context

Error-correction coding is essential to modern communication and storage systems, and its hardware implementation, particularly the decoder, often constitutes the most resource-intensive component of receivers. While high-level synthesis (HLS) tools can automatically generate hardware from high-level descriptions, they often produce designs that are less optimized than hand-crafted ones. Domain-specific hardware autogeneration has proven to be a more effective approach for generating efficient, highly optimized circuits.

Existing works on circuit generation for error correction remain narrow in scope, each supporting only a single code family (e.g., polar codes or LDPC codes) and none featuring a design-space exploration (DSE) optimizer. Developing an open, domain-specific hardware-generation framework that spans multiple families of error-correcting codes and integrates with DSE is an open and impactful research challenge.

This project is part of an NSERC Discovery research program whose long-term objective is to create an open ecosystem for the design-space exploration of error-correction solutions, enabling the informed selection of a code along with the decoding algorithm and hardware architecture, all the way down to the autogeneration of the associated circuits. Furthermore, this program involves collaborations with Prof. François Leduc-Primeau (Polytechnique Montréal), Prof. Camille Leroux (Bordeaux INP, France), and Prof. Stefan Weithoffer (IMT Atlantique, France). Depending on the research direction and the student’s interests, opportunities for co-supervision, close collaboration, or international research stays may be available.

Project Objectives

The primary objective of this project is to investigate, design, and develop domain-specific hardware autogeneration capabilities for error-correction decoders, integrated within a DSE framework.. More specifically, the project aims to:

• Expand domain-specific intermediate representations (IRs) to capture hardware-specific details, including task mapping, dependencies, dataflow, and architecture descriptions, enabling precise hardware synthesis.
• Explore methods for embedding annotations within the IRs to specify hardware constraints and scheduling parameters that guide hardware generation.
• Develop algorithms for translating the IRs into complete domain-specific hardware architectures, encompassing processing units, interconnects, and control logic.
• Investigate methods for mapping tasks to specific hardware components and generating interconnects based on data dependencies, including techniques for parallel data paths and concurrent execution.
• Research automatic control-unit generation, resource-sharing strategies, and optimization techniques such as loop unrolling and pipelining to improve area, throughput, and energy efficiency.
• Develop automated testbench generation to validate hardware accuracy through simulation.